1. Field of the Invention
This invention relates to a semiconductor device and, in particular, to a semiconductor device having a DRAM.
2. Description of Related Art
An SDRAM (Synchronous Dynamic Random Access Memory) performs an operation inside the memory in synchronization with a clock. In the SDRAM, a single data word is exchanged or transferred in one clock. A DDR (Double Data Rate)-SDRAM exchanges data on the rising and the falling edges of a clock so that two data words are sequentially exchanged. Accordingly, the DDR-SDRAM has a data rate twice that of the SDRAM.
In order to minimize an operation delay inside the memory, the DDR-SDRAM uses a DLL (Delay Locked Loop) for generating an internal clock in synchronization with an external clock. For the DLL to properly operate, it is necessary to input the external clock in a proper duty ratio. The “duty ratio” is equivalent in meaning to a ratio of a high level period or a low level period to one cycle period. Herein, the proper duty ratio is 50%. Hereinafter, “duty ratio” is hereinafter called “duty” because those skilled in the art abbreviate “duty ratio” to “duty”. However, the external clock has a duty error (or duty ratio error) because it is impossible to completely remove noise, such as jitter, from the external clock. Therefore, the DLL used in the DDR-SDRAM has a duty determining circuit for detecting and correcting a duty error (or duty ratio error) of the internal clock.
In the DDR-SDRAM, a count value (duty correction condition) of a counter for correcting a duty (or duty ratio) must be frequently updated during a DLL locking period from the start of the DLL to the time when the DLL performs a stable operation. For this purpose, a related-art DDR-SDRAM uses a fixed-cycle duty determining circuit responsive to a determination trigger signal inputted in a predetermined cycle for performing duty detection and determination in the predetermined cycle to produce a determination result and for updating the duty correction condition (count value of the counter for correcting the duty (or duty ratio) on the basis of the determination result.
However, the present inventor has recognized that the use of the above-mentioned fixed-cycle duty determining circuit causes a problem as shown in FIG. 1. Herein, in FIG. 1, each of numeric values specified on input clocks (input CLKs) shows a ratio of a high level period in each cycle period, i.e., a duty ratio.
Referring to FIG. 1, description will be made of a case where the input clocks supplied to the duty determining circuit have jitter fluctuating in a cycle close to a duty determining cycle. In the fixed-cycle duty determining circuit, the duty correction condition is updated in the predetermined cycle. Therefore, during a period between updates (updating operations) of the duty correction condition, duty correction is performed on the basis of a latest duty correction condition obtained in an immediately preceding update.
For example, it is assumed that the duty correction condition is updated at a point “a” in FIG. 1. Then, each clock (input clock) between the point “a” and a point “b” is subjected to duty correction on the basis of a count value of the counter, which is set at the point “a”. In FIG. 1, an input clock at the point “a” has a duty ratio of 45%. Accordingly, a duty correction condition at the point “a” is set to correct a duty (duty ratio) by +5%. Therefore, for all output clocks (output CLKs) between the points “a” and “b”, the duty (duty ratio) is corrected by +5%. Consequently, in a cycle with a duty ratio of 55%, an output clock having a duty ratio of 60% is outputted as a result of correction by +5%, as shown at “A” in FIG. 1.
On the other hand, it is assumed that, at a point “c” in FIG. 1, the duty correction condition is updated on the basis of a clock cycle with a duty ratio of 55%, specifically, a count value of the counter for correcting a duty (duty ratio) is set to correct the duty (duty ratio) by −5%. Then, in a clock cycle with a duty ratio of 45% between the point “c” and a point “d”, an output clock with a duty ratio of 40% is outputted, as shown at “B” in FIG. 1.
As a result of the above-mentioned correction, the input clocks (input CLKs) having the duty ratios varying in a range between 45% and 55% due to jitter are outputted as the output clocks (output CLKs) having the duty ratios varying in a range between 40% and 60%.
JP-A-2006-60842 (Patent Document 1) discloses that, in an abstract, duty cycle correcting amplifiers are employed to produce a DLL output clock having a desired duty cycle of, for example, 50%.